1 commercial and industrial temperature ranges idtcsp5991 programmable skew pll clock driver turboclock gnd/soe 1q 0 skew select 1q 1 1f1:0 3 3 2q 0 skew select 2q 1 2f1:0 fs 3 ref pll fb 3 3q 0 skew select 3q 1 3f1:0 3 3 4q 0 4q 1 skew select 4f1:0 3 3 3 v ccq /pe february 2000 2000 integrated device technology, inc. dsc-5809/- c idtcsp5991 commercial/industrial temperature ranges programmable skew pll clock driver turboclock? description: the csp5991 is a high fanout pll based clock driver intended for high performance computing and data-communications applications. a key feature of the programmable skew is the ability of outputs to lead or lag the ref input signal. the csp5991 has eight programmable skew outputs in four banks of 2. skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. the csp5991 maintains cypress cy7b991 compatibility while pro- viding two additional features: synchronous output enable (gnd/ soe ), and positive/negative edge synchronization (v ccq /pe). when the gnd/ soe pin is held low, all the outputs are synchronously enabled (cy7b991 compatibility). however, if gnd/ soe is held high, all the outputs except 3q0 and 3q1 are synchronously disabled. furthermore, when the v ccq /pe is held high, all the outputs are synchronized with the positive edge of the ref clock input (cy7b991 compatibility). when v ccq /pe is held low, all the outputs are synchro- nized with the negative edge of ref. features: ? 4 pairs of programmable skew outputs ? low skew: 200ps same pair, 250ps all outputs ? selectable positive or negative edge synchronization: excellent for dsp applications ? synchronous output enable ? output frequency: 6.25mhz to 100mhz ? 2x, 4x, 1/2, and 1/4 outputs ? 5v with ttl outputs ? 3 skew grades: csp5991-2: t skew0 <250ps csp5991-5: t skew0 <500ps csp5991-7: t skew0 <750ps ? 3-level inputs for skew and pll range control ? pll bypass for dc testing ? external feedback, internal loop filter ? 46ma i ol high drive outputs ? low jitter: <200ps peak-to-peak ? outputs drive 50 w terminated lines ? pin compatible with cypress cy7b991 ? available in plcc package functional block diagram
2 commercial and industrial temperature ranges idtcsp5991 programmable skew pll clock driver turboclock pin configuration 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 3f 1 4f 0 4f 1 v ccq /pe 4q 1 4q 0 gnd gnd 2f 0 gnd/soe 1f 1 1f 0 1q 0 1q 1 gnd gnd 432 j32-1 1323130 14 15 16 17 18 19 20 3f 0 fs ref gnd test 2f 1 3q 1 3q 0 fb 2q 1 2q 0 v ccn v c c n v c c n v c c q v ccn plcc top view pin description pin name type description ref in reference clock input fb in feedback input test (1) in when mid or high, disables pll (except for conditions of note 1). ref goes to all outputs. skew selections (see control summary table) remain in effect. set low for normal operation. gnd/ soe (1) in synchronous output enable. when high, it stops clock outputs (except 3q 0 and 3q 1 ) in a low state - 3q 0 and 3q 1 may be used as the feedback signal to maintain phase lock. when test is held at mid level and gnd/ soe is high, the nf[ 1:0 ] pins act as output disable controls for individual banks when nf[ 1:0 ] = ll. set gnd/ soe low for normal operation. v ccq /pe in selectable positive or negative edge control. when low/high the outputs are synchronized with the negative/positive edge of the reference clock. nf[ 1:0 ] in 3-level inputs for selecting 1 of 9 skew taps or frequency functions. fs in selects appropriate oscillator circuit based on anticipated frequency range. (see pll programmable skew range.) nq[ 1:0 ] out four banks of two outputs with programmable skew. v ccn pwr power supply for output buffers v ccq pwr power supply for phase locked loop and other internal circuitry gnd pwr ground note: 1. when test = mid and gnd/ soe = high, pll remains active with nf[ 1:0 ] = ll functioning as an output disable control for individual output banks. skew selections remain in effect unless nf[ 1:0 ] = ll. output skew with respect to the ref input is adjustable to compensate for pcb trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked compo- nents. skew is selectable as a multiple of a time unit t u which is of the order of a nanosecond (see pll programmable skew range and resolution table). there are nine skew configurations available for each output pair. these configurations are chosen by the nf 1:0 control pins. in order to minimize the number of control pins, 3-level inputs (high-mid-low) are used, they are intended for but not restricted to hard-wiring. undriven 3-level inputs default to the mid level. where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. the control summary table shows how to select specific skew taps by using the nf 1:0 control pins. programmable skew absolute maximum ratings (1) symbol rating max. unit supply voltage to ground C0.5 to +7 v v i dc input voltage C0.5 to +7 v maximum power dissipation (t a = 85c) 0.8 w t stg storage temperature range C65c to +150c c note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (t a = 25 c, f = 1mhz, v in = 0v) parameter description typ. max. unit c in input capacitance 5 7 pf note: 1. capacitance applies to all inputs except test, fs, and nf1:0.
3 commercial and industrial temperature ranges idtcsp5991 programmable skew pll clock driver turboclock external feedback by providing external feedback, the csp5991 gives users flexibility with regard to skew adjustment. the fb signal is compared with the input ref signal at the phase detector in order to drive the vco. phase differences cause the vco of the pll to adjust upwards or downwards accordingly. notes: 1. the device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. s electing the ap- propriate fs value based on input frequency range allows the pll to operate in its sweet spot where jitter is lowest. 2. the level to be set on fs is determined by the nominal operating frequency of the vco and time unit generator. the vco freque ncy always ap- pears at 1q 1:0 , 2q 1:0 , and the higher outputs when they are operated in their undivided modes. the frequency appearing at the ref and fb inputs will be the same as the vco when the output connected to fb is undivided. the frequency of the ref and fb inputs will be 1/2 or 1/4 the vco frequency when the part is configured for a frequency multiplication by using a divided output as the fb input. 3. skew adjustment range assumes that a zero skew output is used for feedback. if a skewed q output is used for feedback, then a djustment range will be greater. for example if a 4t u skewed output is used for feedback, all other outputs will be skewed C4t u in addition to whatever skew value is programmed for those outputs. max adjustment range applies to output pairs 3 and 4 where 6t u skew adjustment is possible and at the lowest f nom value. 4. the maximum ref clock input frequency is 85mhz. use q/2 or q/4 as feedback and use the control summary table explicitly for output frequency to 100mhz. an internal loop filter moderates the response of the vco to the phase detector. the loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accu- rate responses to input frequency changes. control summary table for feedback signals nf1:0 skew (pair #1, #2) skew (pair #3) skew (pair #4) ll (1) C4t u divide by 2 divide by 2 lm C3t u C6t u C6t u lh C2t u C4t u C4t u ml C1t u C2t u C2t u mm zero skew zero skew zero skew mh 1t u 2t u 2t u hl 2t u 4t u 4t u hm 3t u 6t u 6t u hh 4t u divide by 4 inverted (2) notes: 1. ll disables outputs if test = mid and gnd/ soe = high. 2. when pair #4 is set to hh (inverted), gnd/ soe disables pair #4 high when v ccq /pe= high, gnd/ soe disables pair #4 low when v ccq /pe= low. pll programmable skew range and resolution table fs = low fs = mid fs = high comments timing unit calculation (t u ) 1/(44 x f nom ) 1/(26 x f nom ) 1/(16 x f nom ) vco frequency range (f nom ) (1,2) 25 to 35mhz 35 to 60mhz 60 to 100 mhz (4) skew adjustment range (3) max adjustment: 9.09ns 9.23ns 9.38ns ns 49o 83o 135o phase degrees 14% 23% 37% % of cycle time example 1, f nom = 25mhz t u = 0.91ns t u = 1.54ns example 2, f nom = 30mhz t u = 0.76ns t u = 1.28ns example 3, f nom = 40mhz t u = 0.96ns t u = 1.56ns example 4, f nom = 50mhz t u = 0.77ns t u = 1.25ns example 5, f nom = 80mhz t u = 0.78ns
4 commercial and industrial temperature ranges idtcsp5991 programmable skew pll clock driver turboclock recommended operating range csp5991-5, -7 (industrial) csp5991-2 (commercial) symbol description min. max. min. max. unit vcc power supply voltage 4.5 5.5 4.75 5.25 v t a ambient operating temperature -40 +85 0 +70 c dc electrical characteristics over operating range symbol parameter conditions min. max. unit v ih input high voltage guaranteed logic high (ref, fb inputs only) 2 v v il input low voltage guaranteed logic low (ref, fb inputs only) 0.8 v v ihh input high voltage (1) 3-level inputs only v cc - 1 v v imm input mid voltage (1) 3-level inputs only v cc /2 - 0.5 v cc /2+0.5 v v ill input low voltage (1) 3-level inputs only 1 v i in input leakage current (ref, fb inputs only) v in = v cc or gnd v cc = max. 5a v in = v cc high level 200 i 3 3-level input dc current (test, fs, nf1:0) v in = v cc /2 mid level 50 a v in = gnd low level 200 i pu input pull-up current (v ccq /pe) v cc = max., v in = gnd 100 a i pd input pull-down current (gnd/ soe )v cc = max., v in = v cc 100 a v oh output high voltage v cc = min., i oh = - 16ma 2.4 v v cc = min., i oh = - 40ma v v ol output low voltage v cc = min., i ol = 46ma 0.45 v i os output short circuit current (2) v cc = max., v o = gnd - 250 ma notes: 1. these inputs are normally wired to v cc , gnd, or unconnected. internal termination resistors bias unconnected inputs to v cc /2. if these inputs are switched, the function and timing of the outputs may be glitched, and the pll may require an additional t lock time before all datasheet limits are achieved. 2. this is to be measured at 25c with 10:1 duty cycle, one output at a time, and one second maximum. power supply characteristics symbol parameter test conditions typ. max. unit i ccq quiescent power supply current v cc = max., test = mid, ref = low, gnd/ soe = low, all outputs unloaded 10 40 ma d i cc power supply current per input high v cc = max., v in = 3.4v 0.4 1.5 ma i ccd dynamic power supply current per output v cc = max., c l = 0pf 100 160 m a/mhz i tot total power supply current v cc = 5v, f ref = 20mhz, c l = 240pf (1) 43 ma v cc = 5v, f ref = 33mhz, c l = 240pf (1) 63 ma v cc = 5v, f ref = 66mhz, c l = 240pf (1) 117 ma note: 1. for eight outputs, each loaded with 30pf.
5 commercial and industrial temperature ranges idtcsp5991 programmable skew pll clock driver turboclock notes: 1. all timing tolerances apply for f nom > 25mhz. 2. skew is the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with the specified load. 3. t skewpr is the skew between a pair of outputs (xq 0 and xq 1 ) when all eight outputs are selected for 0t u . 4. t skew0 is the skew between outputs when they are selected for 0t u . 5. there are 3 classes of outputs: nominal (multiple of t u delay), inverted (4q 0 and 4q 1 only with 4f 0 = 4f 1 = high), and divided (3qx and 4qx only in divide-by-2 or divide-by-4 mode). 6. t dev is the output-to-output skew between any two devices operating under the same conditions (v cc , ambient temperature, air flow, etc.) 7. t lock is the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits. 8. t pd is measured with ref input rise and fall times (from 0.8v to 2.0v) of 1.0ns. 9. measured at 2.0v. 10. measured at 0.8v. 11. refer to input timing requirements table for more detail. input timing requirements symbol description (1) min. max. unit t r , t f maximum input rise and fall times, 0.8v to 2v 10 ns/v t pwc input clock pulse, high or low 3 ns d h input duty cycle 10 90 % r ef reference clock input 10 85 mhz note: 1. where pulse width implied by d h is less than t pwc limit, t pwc limit applies. switching characteristics over operating range csp5991-2 csp5991-5 csp5991-7 symbol parameter min. typ. max. min. typ. max. min. typ. max. unit f nom vco frequency range see pll programmable skew range and resolution table t rpwh ref pulse width high (1) 3 3 3 ns t rpwl ref pulse width low (1) 3 3 3 ns t u programmable skew time unit see skew selection table for output pairs t skewpr zero output matched-pair skew (xq 0 , xq 1 ) (1,2, 3) 0.05 0.2 0.1 0.25 0.1 0.25 ns t skew0 zero output skew (all outputs) c l = 0pf (1, 4) 0.1 0.25 0.25 0.5 0.3 0.75 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) (1, 3) 0.25 0.5 0.6 0.7 0.6 1 ns t skew2 output skew (rise-fall, nominal-inverted, divided-divided) (1, 5) 0.5 01.2 0.5 1.2 0.5 1.5 ns t skew3 output skew (rise-rise, fall-fall, different class outputs) (1, 5) 0.25 0.5 0.5 0.7 0.7 1.2 ns t skew4 output skew (rise-fall, nominal-divided, divided-inverted) (1, 2) 0.5 0.9 0.5 1 1.2 1.7 ns t dev device-to-device skew ( 1,2, 6) 0.75 1.25 1.65 ns t pd ref input to fb propagation delay ( 1,8) - 0.25 00.25 - 0.5 00.5 - 0.7 00.7ns t odcv output duty cycle variation from 50% (1) - 1.2 01.2 - 1.2 01.2 - 1.2 01.2ns t pwh output high time deviation from 50% (1,9) 2 2.5 3 ns t pwl output low time deviation from 50% (1,10) 2.5 3 3.5 ns t orise output rise time (1) 0.15 1 1.5 0.15 1 1.5 0.15 1.5 2.5 ns t ofall output fall time (1) 0.15 1 1.5 0.15 1 1.5 0.15 1.5 2.5 ns t lock pll lock time (7) 0.5 0.5 0.5 ms t jr cycle-to-cycle output jitter rms 25 25 25 ps peak-to-peak 200 200 200
6 commercial and industrial temperature ranges idtcsp5991 programmable skew pll clock driver turboclock ac test loads and waveforms 2.0v t pwl t pwh t orise t ofall 0.8v 1ns 1ns 2.0v 0.8v 3.0v 0v vth = 1.5v 130 w 91 w v cc output c l = 50pf (c l = 30pf for -2 and -5 devices) c l test load ttl output waveform ttl input test waveform
7 commercial and industrial temperature ranges idtcsp5991 programmable skew pll clock driver turboclock ref fb q other q inverted q ref divided by 2 ref divided by 4 t ref t pd t skewpr t skew0, 1 t skew2 t skew3, 4 t skew1, 3, 4 t skew2, 4 t skew3, 4 t skew3, 4 t skew2 t skewpr t skew0, 1 t jr t odcv t odcv t rpwh t rpwl ac timing diagram notes: v ccq /pe: the ac timing diagram applies to v ccq /pe=v cc . for v ccq /pe=gnd, the negative edge of fb aligns with the negative edge of ref, divided outputs change on the negative edge of ref, and the positive edges of the divide-by-2 and the divide-by-4 signals align. skew: the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with 50pf (30pf for -2 and -5) and terminated with 50 w to 2.06v. t skewpr : the skew between a pair of outputs (xq 0 and xq 1 ) when all eight outputs are selected for 0t u . t skew0 : the skew between outputs when they are selected for 0t u . t dev : the output-to-output skew between any two devices operating under the same conditions (v cc , ambient temperature, air flow, etc.) t odcv : the deviation of the output from a 50% duty cycle. output pulse width variations are included in t skew2 and t skew4 specifications. t pwh is measured at 2.0v. t pwl is measured at 0.8v. t orise and t ofall are measured between 0.8v and 2.0v. t lock : the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits.
8 commercial and industrial temperature ranges idtcsp5991 programmable skew pll clock driver turboclock corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. turboclock is a registered trademark of integrated device technology, inc. ordering information idtcsp xxxxx xx x package process device type blank i 5991-2 5991-5 5991-7 programmable skew pll clock driver turboclock rectangular plastic leaded chip carrier (j32-1) jr commercial (0c to +70c) industrial (-40c to +85c)
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